1. Field of the Invention
The present invention relates to a bus system, and more particularly, to a method of using a bus capable of efficiently transferring a large amount of data and a bus interface in a bus system.
2. Description of Related Art
Referring to FIG. 1, a conventional bus system includes masters A-D respectively denoted by reference numerals 11-14, a video processor 15, a video display 16, a bus arbiter 17, a memory controller 18, and a memory 19. In the following description, the video processor 15 corresponds to a master, and the memory 19 corresponds to a slave. The memory controller 18 is a unit for controlling only the memory 19, and is installed in a front end of the memory 19. All the data transferred to the memory 19 pass through the memory controller 18 and then arrive at the memory 19. Therefore, the memory controller 18 instead of the memory 19 has been typically called a slave. Hereinafter, the memory controller 18 will be called a slave. Otherwise, a memory 19 will be called a slave in a special case. A line which connects masters 11-14 with the memory controllers corresponding to a slave is called a bus. Such a bus is composed of an address bus which loads (or carries) addresses, a control bus which loads control signals, and a data bus which loads data.
The masters 11-14 are units which actively use the bus. The masters 11-14 generate addresses and control signals needed to transmit data by way of the bus, and send bus use requests to the bus arbiter 17. Then, the addresses are loaded on the address bus, and control signals are loaded on the control bus when use is granted by the bus arbiter 17 which receives the bus use request. In addition, data are loaded on a data bus when a response signal is received.
The bus arbiter 17 receives a bus use request from each of the masters 11-15 and grants permission to each of the masters 11-15. Typically, since the bus can be used by only one master at a time, only one of the masters 11-15 is granted the use permission at a time based on the order of the use requests and priorities of the masters 11-15. The memory controller 18 corresponding to a slave is a unit which passively uses the bus. The memory controller 18 receives addresses and control signals transmitted from the master which has been granted the use permission by the bus arbiter 17, and transmits a response signal to the masters 11-15.
According to the above conventional bus system, two kinds of waiting times are needed to complete a cycle of data transmission. That is, a waiting time for transmitting addresses and control signals from the master obtaining the use permission as a result of arbitrating the bus to the memory controller 18 corresponding to a slave, and the other waiting time for reading/writing data from a memory controller 18 corresponding to a slave to the memory 19 corresponding to the destination. As a result, during the waiting time the bus is not used and bus use efficiency is degraded. In addition, when a plurality of masters send bus use requests at the same time, a bottleneck is generated which causes increased waiting times.